Checkpoint Processing and Recovery: An Efficient, Scalable Alternative to Reorder Buffers

0272-1732/03/$17.00  2003 IEEE Published by the IEEE computer Society Achieving high performance in modern microprocessors requires a combination of exposing large amounts of instruction level parallelism (ILP) and processing instructions at a high clock frequency. Exposing maximum ILP requires the processor to operate concurrently on large numbers of instructions, also known as the instruction window; a highfrequency design requires frequently accessed structures to be small and fast. These requirements are somewhat at odds with each other— hardware structures must be sufficiently large to buffer and process all instructions in a large instruction window, yet must remain fast enough to support high frequencies. Thus, new designs that focus on eliminating large, cycle-critical hardware structures become necessary to achieve high performance. We have proposed Checkpoint Processing and Recovery (CPR) as an efficient microarchitecture capable of sustaining large instruction windows without requiring large critical structures. In our original work, we presented a detailed study of performance issues for large instruction windows in addition to a CPR design. Here, we focus on an out-oforder processor with a reorder buffer (ROB). In conventional designs, each instruction in the instruction window must have an entry in the ROB. We argue that to build scalable, large instruction windows, future processors must move away from a ROB-centric design Haitham Akkary